The present invention relates generally to a semiconductor device and its method of manufacture, and more particularly to a semiconductor device having a gate electrode with a high aspect ratio and a narrow pitch, preferably a dynamic random access memory (DRAM).
It remains a continuing goal of semiconductor manufacturing to fabricate devices with smaller and smaller features. One such feature can include a transistor gate length. As gate lengths approach smaller and smaller sizes, transistors can suffer from the unwanted generation of hot carriers, which can lead to xe2x80x9cshortxe2x80x9d channel effects. Short channel effects can reduce the reliability of transistors.
One approach to addressing reduced reliability from short channel effects can include reducing the electric field region in the vicinity of a transistor drain. A structure for reducing such an electric field can include a lightly doped drain (LDD). An LDD structure can include a region between a channel (situated below a transistor gate) and a source/drain region that has a lower impurity density than the source/drain region. Such a structure can result in a less severe, or milder impurity density than non-LDD structures. This can raise a punch-through voltage and/or hot carrier withstand voltage in a transistor, thus improving reliability.
Japanese Laid-Open Patent Application Nos. 226499/1995, 074196/1997 and 45995/1999 disclose a structure that includes an LDD region. In the disclosed structure, a silicon oxide film, a silicon nitride film, or a reoxidizied nitrided oxide (RNO) can be formed on a gate electrode side wall.
Japanese Laid-Open Patent Application No. 226499/1995 also discloses an oxide film that covers a gate electrode. The oxide film can improve product yield by recovering a damaged gate oxide film to an original condition.
Referring now to FIGS. 1(a) to 1(d), a series of cross sectional views are shown illustrating a conventional method for manufacturing a semiconductor device. The method of FIGS. 1(a) to 1(d) can correspond to that shown in Japanese Laid-Open Patent Application No. 226499/1995.
Referring now to FIG. 1(a), a device isolation film (not shown) is formed on a semiconductor substrate 1. Substrate 1 may be p-type silicon. A gate oxide film 5 may be formed in a field (or active) region with a thermal oxidation method. A field region may be surrounded by a device isolation film, which may include silicon oxide. Thereafter, polysilicon may be formed on the gate oxide film 5 with a reduced pressure chemical vapor deposition (CVD) method. A gate electrode 6 may be formed from the polysilicon with known photolithography and dry etching techniques.
Next, as shown in FIG. 1(b), an oxide film 13 is formed that covers gate electrode 6 with a heat treatment in an oxygen atmosphere. As noted before, oxide film 13 can recover gate oxide film 5 that has been damaged.
Thereafter, as shown in FIG. 1(c), an entire surface of a substrate 1 is implanted with low density ions, with ion implantation techniques. Gate electrode 6 may be an implant mask. Annealing under predetermined conditions may result in Nxe2x88x92 type source/drain region 3.
Then, as shown in FIG. 1(d), a silicon oxide film, etc., is deposited on the entire surface of the substrate 1 with reduced pressure CVD methods, or the like. The silicon oxide film may then be etched back with anisotropic dry etching to form side wall oxide film 14 on a side wall of gate electrode 6. A high density ion implantation may then be performed with gate electrode 6 and side wall oxide film 14 as masks, to form N+ source/drain region 4.
In a resulting structure, a low density impurity region (e.g., Nxe2x88x92 type source/drain region 3) may be formed that is offset with respect to a gate electrode 6. Such a low density impurity region may also be self-aligned with a gate electrode 6, just under side wall oxide film 14. At the same time, a high density impurity region may (e.g., N+ type source/drain region 4) is formed on the outside of side wall oxide film 14.
In a conventional approach like that described above, a substrate region below an end of a gate electrode 6 may not be implanted, and thereby not form a portion of a low density impurity region. This may be particularly true when a side surface film, such as an oxide film and/or nitride film, is formed on a side of a gate electrode 6. Such a side surface film (like 13) may block ions from penetrating into a substrate. Thus, a substrate region offset with respect to a gate electrode 6 is prevented from being effectively implanted. Due to such a non-implanted region, a resulting source/drain region may have a higher than desirable resistance, unduly slowing the speed of a metal-oxide-semiconductor (MOS) transistor.
To solve the problem of high resistance offset regions, a method is disclosed in Japanese Laid-Open Patent Application Nos. 074196/1997 and 012747/1998. The method shows forming Nxe2x88x92 type source/drain regions with a low density impurity implantation having a tilted implant angle. That is, impurities are implanted at a slant with respect to a normal line of a substrate. Such tilt implant approaches can address the problem of failing to implant close enough to a gate electrode for certain device features. However, as feature sizes shrink and/or are changed, such methods may not be sufficient.
As features sizes shrink, a width of a sidewall oxide film (such as that shown as 14 in FIG. 1(d)) can also shrink. This may be desirable in order to increase a contact area. A smaller sidewall thickness, however, may translate into a smaller interval between a channel region and a higher density impurity region of a source/drain formed outside a side wall oxide film. This reduced interval may result in a leakage current due to a strong electric field at the end of a gate, and thus reduce the data retention times of a transistor.
In addition, in many cases a gate electrode 6 can have a laminated structure that includes a polysilicon layer and a silicide layer. Such laminated gate electrodes may have a greater height, further increasing an aspect ratio (height/width) of a gate electrode. The above noted problem of an undesirably narrow interval may be more conspicuous for higher aspect ratio structures.
To better understand the drawbacks to conventional approaches, a conventional manufacturing method for a semiconductor device will now be described with reference to FIGS. 2(a)-2(e). FIGS. 2(a)-2(e) show cross sectional views of a semiconductor device having structures with high aspect ratios.
Referring first to FIG. 2(a), a device isolation film 2 is formed in a semiconductor substrate 1. A semiconductor substrate 1 can comprise p type silicon, or the like, and a device isolation film 2 may be an oxide. A gate insulating film 5 comprising silicon oxide may be formed on a semiconductor substrate 1 with a thermal oxidation method. A gate insulating film 5 may cover a field region situated between device isolation films 2. Thereafter, a polysilicon film 6a and silicide film 6b may be formed using a plasma CVD (PCVD) method, or the like. A mask nitride film 15 may then be formed. A mask nitride film 15 may serve as an etch stop that can prevent a silicide film 6b from being exposed in a side wall etch back step (described more below). A patterning step may then etch through a mask nitride film 15, silicide film 6b, and polysilicon film 6a to form a gate electrode 6. Such a patterning step includes known photolithography and dry etching steps.
In addition to protecting a gate 6, during an etch back step that forms side wall oxide layers, a mask nitride film 15 can also serve as an etch stop in a self-aligned contact structure. In a self-aligned contact structure, a contact hole may overlap a gate electrode 6. During a contact hole etching step, side wall oxide layers and top mask nitride film prevent a gate electrode 6 from being exposed. In order to ensure such protection of a gate electrode 6, a mask nitride may have a certain minimum thickness. Such a mask nitride film 15 thickness may further contribute to the aspect ratio of a resulting gate structure.
Referring now to FIG. 2(b), exposed portions of a substrate are implanted with a low density impurity ion. Gate electrode 6 and mask nitride film 15 may act as implant masks. As represented by arrows in FIG. 2(b), such an ion implantation may be a tilt implantation (implant at a slant with respect to a substrate 1). As a result, substrate regions in the vicinity of a gate electrode 6, that might otherwise not be implanted with a conventional non-tilt implant, can be implanted with an impurity ion. This can eliminate the high resistance offset region noted above. After an annealing step, low density LDD type source/drain regions can be formed. For example, an Nxe2x88x92 source/drain region 3 is formed.
Referring now to FIG. 2(c), a silicon oxide film, or the like, is deposited over the entire surface of a substrate 1. Such a deposition can include a reduced pressure CVD method, or the like. A resulting silicon oxide film is then etched back, with anisotropic dry etching, to form side wall oxide film 14 on the side wall of gate electrode 6 and mask nitride film 15. It is noted that in such an etchback step, a mask nitride film 15 can serve as an etch stop, protecting a gate electrode 6 from being exposed.
Referring now to FIG. 2(d), exposed portions of a substrate are implanted with a high density impurity ion. Gate electrode 6, mask nitride film 15, and side wall oxide film 14 serve as implant masks. After an annealing step, high density source/drain regions can be formed. For example, an N+ source/drain region 4 is formed.
Referring now to FIG. 2(e), a contact plug 10 is formed in regions between adjacent side wall oxide films 14. An interlayer insulating film, such as a borophosphosilicate glass (BPSG) film 11, can be formed over a contact plug. Contact holes may be formed in a BPSG film 11 and a conductor may be formed in such contact holes. In FIG. 2(e), a bit contact hole 12a and capacitive contact hole 12b may be formed in a BPSG film 11. In this way, a semiconductor device may be partially completed.
The above conventional approach shows how low density impurity regions can be formed in close proximity to the end of a gate electrode 6 with a tilt implant. However, at the same time, a side wall oxide film 14 thickness may be reduced to ensure sufficient area between a contact plug 10 and N+ source/drain region 3 and/or due to a high aspect ratio of a gate electrode 6. As a result, as shown in FIG. 2(e), a distance between a contact plug 10 and the end of a gate electrode 6 (shown as xe2x80x9cNARROW INTERVALxe2x80x9d) can become small. This reduction in the interval size can result in the deterioration of data retention characteristics of a resulting transistor due to leakage current.
It would be desirable to arrive at some way of preventing the data retention characteristics of a transistor from being degraded due to decreased size of an interval between a contact plug and an end of a gate electrode.
A semiconductor device according to the present invention may include a gate electrode having a reverse tapered shape when viewed in cross section. A reverse tapered shape may be formed by etching a lower layer of laminate gate electrode into a reverse tapered shape. In addition, or alternatively, a side surface insulating film may be formed on the side of a gate electrode that is thicker on the sides of an upper layer of the gate electrode than on the sides of a lower layer of a gate electrode.
With a reverse tapered shape in a gate electrode, a semiconductor device can include a greater interval distance between the edge of a gate electrode and a contact plug. Such greater interval may be achieved even for semiconductor devices having reduced pitch and gate electrodes with a high aspect ratio. In addition, a low- or non-doped offset region at the end of a gate electrode may be prevented from being formed. Thus, leakage current may be reduced and a data retention time of a resulting transistor may be improved.
According to one aspect of the embodiments, a lower layer of a gate electrode may include polysilicon while an upper layer may include a silicide, such as tungsten silicide.
According to another aspect of the embodiments, a side surface insulating film may be formed by oxidizing a gate electrode. Such an oxidation may occur at a temperature between 1000 and 1100xc2x0 C.
According to another aspect of the invention, a mask insulating layer may be formed on a top of a gate electrode and a side wall insulating film may be formed on sides of a mask insulating layer and a gate electrode. A mask insulating layer may include silicon oxide while a side wall insulating film may include silicon nitride.
According to another aspect of the embodiments, gate electrode, including a corresponding side surface insulating film, may have a particular inclination angle with respect to a substrate. In particular, a line can be conceptualized as being drawn from an outer edge of a side surface insulating film on the side of an upper layer to an outer edge of a side surface insulating film on the side of a lower layer. Such a line may have an incidence angle that is no greater than 15xc2x0 with respect to a normal to the substrate. Preferably, an incidence angle may be about 7xc2x0.
According to another aspect of the embodiments, a first (lower) density impurity region may be formed, at least in part, by a tilt impurity implant with a gate electrode and side surface insulating film as a mask. A tilt angle may preferably be coincident with an angle of incidence of a gate electrode.
According to another aspect of the embodiments, a second (higher) density impurity region may be formed, at least in part, by an impurity implant with a gate electrode and side wall insulating film as a mask.
According to another aspect of the embodiments, a contact plug may be formed between side wall insulating films on sides of adjacent gate electrodes.